Operational amplifiers (op-amps) may be time-shared by different parts of a circuit, such as between pipelined analog to digital converter (ADC) stages or between different slices in time-interleaved ADCs. In such time-sharing op-amp schemes, a multiplexer provides the inputs from the different parts of the circuit to the shared op-amp. However, the internal circuit nodes of the multiplexer and the op-amp may have a memory of previous signals applied from shared parts of the circuit, resulting in cross-talk that degrades accuracy.
As a conventional approach for eliminating the memory effect, an explicit and separate reset phase may be added to the ADC non-overlapping clock scheme. During the reset phase, a neutral voltage such as a common mode voltage may be applied to the op-amp input. The op-amp is effectively idle during the reset phase, and the circuit nodes are brought back to a quiescent state to remove any memory of prior signals. However, to completely eliminate the memory effect, the reset phase must occupy a significant portion of the clock cycle. As a consequence, the reset phase significantly reduces the time available for op-amp settling for a given clock speed, resulting in increased power consumption or a lower sampling rate.
Therefore, there is a need for a method of reducing memory effect in circuits such as pipelined ADCs with op-amp sharing, that shortens or eliminates the explicit reset phase between different slices to improve sampling rate, and that eliminates inter-symbol interference between stages.